1. Field of the Invention
The present invention relates to a thin film magnetic memory device, and particularly to a thin film magnetic memory device provided with memory cells having MTJs (magnetic tunnel junctions)
2. Description of the Background Art
Attention is being given to an MRAM device as a memory device, which can nonvolatilely store data with low power consumption. The MRAM device is a memory device, in which a plurality of thin film magnetic members are formed in a semiconductor integrated circuit for nonvolatilely storing data, and the thin film magnetic members serve as memory cells allowing random access, respectively.
Particularly, in recent years, it has been announced that a performance of the MRAM device can be dramatically improved by using the thin film magnetic members, which utilize the magnetic tunnel junctions, as memory cells. The MRAM device with memory cells having the magnetic tunnel junctions has been disclosed in technical references such as xe2x80x9cA 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cellxe2x80x9d, ISSCC Digest of Technical Papers, TA7.2, February 2000, xe2x80x9cNonvolatile RAM based on Magnetic Tunnel Junction Elementsxe2x80x9d, ISSCC Digest of Technical Papers, TA7.3, February 2000, and xe2x80x9cA 256 kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAMxe2x80x9d, ISSCC Digest of Technical Papers, TA7.6, February 2001.
FIG. 18 conceptually shows a structure of a memory cell, which has a magnetic tunneling junction, and may be merely referred to as an xe2x80x9cMTJ memory cellxe2x80x9d hereinafter.
Referring to FIG. 18, a MTJ memory cell includes a tunneling magneto-resistance element TMR having an electric resistance, which is variable in accordance with a data level of magnetically written storage data, and an access transistor ATR. Access transistor ATR is located between a bit line BL and a ground voltage GND, and is connected in series to tunneling magneto-resistance element TMR. Typically, access transistor ATR is formed of a field-effect transistor arranged on a semiconductor substrate.
For the MTJ memory cell, the device includes bit line BL and a digit line DL for carrying a data write current in different directions during a data write operation, respectively, as well as a word line WL for instructing data reading. In the data read operation, tunneling magneto-resistance element TMR is electrically coupled between ground voltage GND and bit line BL in response to turn-on of access transistor ATR.
FIG. 19 conceptually shows an operation of writing data in the MTJ memory cell.
Referring to FIG. 19, tunneling magneto-resistance element TMR has a ferromagnetic material layer FL, which has a fixed and uniform magnetization direction, and may be merely referred to as insulator a xe2x80x9cfixed magnetic layerxe2x80x9d hereinafter, and a ferromagnetic material layer VL, which is magnetized in a direction depending on an externally applied magnetic field, and may be merely referred to as a xe2x80x9cfree magnetic layerxe2x80x9d hereinafter. A tunneling barrier (tunneling film) TB formed of an insulator film is disposed between fixed magnetic layer FL and free magnetic layer VL. Free magnetic layer VL is magnetized in the same direction as fixed magnetic layer FL or in the opposite direction in accordance with the level of the storage data to be written. Fixed magnetic layer FL, tunneling barrier TB and free magnetic layer VL form a magnetic tunneling junction.
Tunneling magneto-resistance element TMR has an electric resistance, which is variable depending on a correlation in magnetization direction between fixed magnetic layer FL and free magnetic layer VL. More specifically, the electric resistance value of tunneling magneto-resistance element TMR takes a minimum value Rmin when the magnetization directions of fixed magnetic layer FL and free magnetic layer VL are parallel to each other. When the magnetization directions of them are opposite (parallel opposite) to each other, the above electric resistance value takes a maximum value Rmax.
In the data write operation, word line WL is inactive, and access transistor ATR is off. In this state, the data write currents for magnetizing free magnetic layer VL are supplied to bit line BL and digit line DL in directions depending on the level of write data, respectively.
FIG. 20 conceptually shows a relationship between the data write current and the magnetization direction of the tunneling magneto-resistance element in the data write operation.
Referring to FIG. 20, an abscissa H(EA) gives a magnetic field, which is applied along an easy axis (EA) to free magnetic layer VL of tunneling magneto-resistance element TMR. An ordinate H(HA) indicates a magnetic field acting along a hard axis (HA) on free magnetic layer VL. Ordinate H(HA) and abscissa H(EA) correspond to two magnetic fields produced by currents flowing through bit line BL and digit line DL, respectively.
In the MTJ memory cell, the fixed magnetization direction of fixed magnetic layer FL is parallel to the easy axis of free magnetic layer VL, and free magnetic layer VL is magnetized in the direction of the easy axis, and particularly in the same parallel direction, which is the same direction as fixed magnetic layer FL, or in the opposite parallel direction, which is opposite to the above direction, depending on the level (xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d) of the storage data. The MTJ memory cell can selectively store data (xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d) of one bit corresponding to the two magnetization directions of free magnetic layer VL.
The magnetization direction of free magnetic layer VL can be rewritten only when a sum of applied magnetic fields H(EA) and H(HA) falls within a region outside an asteroid characteristic line shown in FIG. 20. Therefore, the magnetization direction of free magnetic layer VL does not change when the data write magnetic fields applied thereto have intensities corresponding to a region inside the asteroid characteristic line.
As can be seen from the asteroid characteristic line, the magnetization threshold required for changing the magnetization direction along the easy axis can be lowered by applying the magnetic field in the direction of the hard axis to free magnetic layer VL.
When the operation point in the data write operation is designed, for example, as shown in FIG. 20, the data write magnetic field in the MTJ cell selected as a data write target is designed such that the data write magnetic field in the direction of the easy axis has an intensity of HWR. Thus, the data write current flowing through bit line BL or digit line DL is designed to take a value, which can provide the data write magnetic field of HWR. In general, data write magnetic field HWR is represented by a sum of a switching magnetic field HSW required for switching the magnetization direction and a margin xcex94H. Thus, it is represented by an expression of
HWR=HSW+xcex94H.
For rewriting the storage data of the MTJ memory cell, i.e., the magnetization direction of tunneling magneto-resistance element TMR, it is necessary to pass the data write currents at a predetermined level or higher through digit line DL and bit line BL. Thereby, free magnetic layer VL in tunneling magneto-resistance element TMR is magnetized in the same parallel direction as fixed magnetic layer FL or opposite parallel direction in accordance with the direction of the data write magnetic field along the easy axis (EA). The magnetization direction, which was once written into tunneling magneto-resistance element TMR, and thus the storage data of MTJ memory cell is held nonvolatilely until next data writing is executed.
FIG. 21 conceptually shows an operation of reading data from the MTJ memory cell.
Referring to FIG. 21, access transistor ATR is turned on in response to activation of word line WL in the data read operation. Thereby, tunneling magneto-resistance element TMR is electrically coupled to bit line BL while being pulled down with ground voltage GND.
In this state, bit line BL is pulled up with a predetermined voltage, whereby a current path including bit line BL and tunneling magneto-resistance element TMR carries a memory cell current Icell corresponding to the electric resistance of tunneling magneto-resistance element TMR, and thus corresponding to storage data of the MTJ memory cell. For example, this memory cell current Icell is compared with a predetermined reference current, whereby storage data can be read out from the MTJ memory cell.
As described above, the electric resistance of tunneling magneto-resistance element TMR is variable in accordance with the magnetization direction, which is rewritable by the data write magnetic field applied thereto. Therefore, nonvolatile data storage can be executed by establishing a correlation of electric resistances Rmax and Rmin of tunneling magneto-resistance element TMR with respect to levels (xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d) of the storage data.
As described above, the MRAM device executes the data storage by utilizing a difference xcex94R (=Rmaxxe2x88x92Rmin) in junction resistance of tunneling magneto-resistance element TMR corresponding to a difference between storage data levels. Thus, the data read operation is executed based on the detection of passing current Icell of the selected memory cell.
FIG. 22 conceptually shows a conventional data read circuit.
The following description is given on an operation of reading data from memory cells arranged in rows and columns, and particularly from the memory cell storing data of one bit.
Referring to FIG. 22, complementary bit lines are alternately arranged corresponding to memory cell columns. In FIG. 22, the MTJ memory cells are arranged corresponding to each of bit lines BL and /BL, respectively. The above symbol xe2x80x9c/xe2x80x9d represents inversion, negation, complement or the like in this specification. Each of the MTJ memory cells has a structure similar to that shown in FIG. 18, and has tunneling magneto-resistance element TMR and access element (transistor) ATR connected in series between corresponding bit line BL or /BL and ground voltage GND. Access transistor ATR is connected to corresponding word line WL.
In the following description, one of the two MTJ memory cells, which is connected to bit line BL is merely referred to as xe2x80x9cmemory cell MCxe2x80x9d, and the other connected to bit line /BL is referred to as a xe2x80x9creference cell/MCxe2x80x9d. Memory cell MC and reference cell /MC execute the storing of data of one bit. More specifically, storage data is written into memory cell MC, and data complementary with that in memory cell MC is written into reference cell /MC.
Local data lines LIO and /LIO are arranged for transmitting read data. Local data lines LIO and /LIO form a local data line pair LIOP. In the following description, each of local data lines LIO and /LIO is merely referred to as a xe2x80x9cdata linexe2x80x9d. Local data line pair LIOP is merely referred to as a xe2x80x9cdata line pair LIOPxe2x80x9d.
The structure is further provided with a data amplifier circuit 90 for amplifying a difference between passing currents, which pass through data lines LIO and /LIO, respectively, and outputting it as data. Data amplifier circuit 90 is activated in response to activation signal SER, and thereby amplifies the passing current difference in the data read operation.
In each memory cell column, column select gate CSG is arranged between the ends on the other side of bit lines BL and /BL and data lines LIO and /LIO. Column select gate CSG is turned on in response to activation (xe2x80x9cHxe2x80x9d level) of corresponding column select line CSL. Column select line CSL is activated (xe2x80x9cHxe2x80x9d level) in the selected column during either of the data writing and data reading.
An equalize circuit EQG is provided for each memory cell column. Equalize circuit EQG has a transistor switch 31 connected between corresponding bit lines BL and /BL, a transistor switch 32 connected between bit line BL and ground voltage GND, and a transistor switch 33 connected between bit line /BL and ground voltage GND. Each of transistor switches 31-33 is formed of, e.g., an N-channel MOS transistor.
Each of transistor switches 31-33 receives on its gate a bit line equalize signal BLEQ common to the memory cell column. Bit line equalize signal BLEQ is activated to attain xe2x80x9cHxe2x80x9d level at least during a predetermined period before the data read operation.
FIG. 23 is a timing chart illustrating an operation of each internal circuit during data reading by the conventional data read circuit system.
Referring to FIG. 23, bit line equalize signal BLEQ is at xe2x80x9cHxe2x80x9d level, and bit lines BL and /BL are in the state precharged to ground voltage GND before start of the data reading at time tA. When the data reading starts at time tA, bit line equalize signal BLEQ attains xe2x80x9cLxe2x80x9d level, and is isolated or disconnected from ground voltage GND.
At a time tB, word line WL is activated to attain xe2x80x9cHxe2x80x9d level so that access transistors ATR are turned on to couple electrically bit lines BL and /BL to ground voltage GND. Column select gate CSG is turned on in response to activation (xe2x80x9cHxe2x80x9d level) of column select line CSL so that data lines LIO and /LIO are electrically coupled to bit lines BL and /BL, respectively.
At a time tC when a period tWL elapses from time tB, an activating signal SER of data amplifier circuit 90 is activated (xe2x80x9cLxe2x80x9d level) so that a data read current is supplied for starting charging of bit lines BL and /BL and data lines LIO and /LIO.
After time tC, a voltage difference allowing detection of a data level does no occur between read data OUT and /OUT until a passing current difference occurs to an extent, which allows detection of the data read current.
By supplying the data read current from data amplifier circuit 90, charging of bit lines BL and /BL and data lines LIO and /LIO is completed at a time tD. After about this time tD, it becomes possible to detect the passing current difference, i.e., the resistance difference based on the storage data of the memory cell MC so that data amplifier circuit 90 produces a voltage difference xcex94V. The storage data is read out based on this voltage difference xcex94V between read data OUT and /OUT.
As described above, a period of time tBL (between times tC and tD) for charging the bit lines and data lines is required after start of the data reading and before output of the storage data of memory cell MC.
In particular, load capacitances and therefore the charging times of data lines LIO and /LIO generally increase with increase in capacity of the memory array. The charging times of the data lines in the data read operation impair an operation speed of the data reading.
An object of the invention is to provide a thin film magnetic memory device, which can reduce a charging time of data lines and bit lines required after start of data reading, and can perform fast data reading.
According to an aspect of the invention, a thin film magnetic memory device includes a plurality of memory cells, a word line, first and second data lines and a differential amplifier portion. Each of the plurality of memory cells has an electric resistance corresponding to magnetically written storage data. The word line is activated when the data is to be read from the selected memory cell among the plurality of memory cells. The first data line is electrically coupled to the first voltage via the selected memory cell during the data reading. The second data line is electrically coupled to a first voltage via a reference cell provided as a comparison target of the selected memory cell during the data reading. The differential amplifier portion is activated prior to the word line during the data reading to couple electrically each of the first and second data lines to a second voltage, to start supply of a current to the first and second data lines and to perform data reading in accordance with a difference between currents passing through the first and second data lines, respectively.
Accordingly, the invention can achieve the following major advantage. In the data read operation, the differential amplifier portion is activated before a current path including the data line and the selected memory cell is formed in accordance with activation of the word line, and thereby the differential amplifier electrically couples the second voltage to the data lines to start the charging of the data lines. Since the charging of the data line is completed early, it is possible to reduce a time required from start of the data reading to a time, when the passing current difference between the data lines reaches a level corresponding to the storage data of the selected memory cell, and the data reading can be performed fast.
According to another aspect of the invention, a thin film magnetic memory device includes a plurality of memory cells, a reference cell, first and second data lines, a level control circuit and a data read circuit. Each of the plurality of memory cells has one of first and second electric resistances corresponding to magnetically written storage data. The reference cell has an electric resistance intermediate between the first and second electric resistances. The first data line is electrically coupled between first and second voltages via the selected memory cell corresponding to a selected address among the plurality of memory cells during data reading. The second data line is electrically coupled between the first and second voltages via the reference cell during the data reading. The level control circuit is provided corresponding to the first and second data lines for changing levels of the first and second data lines to predetermined levels during the data reading. The data read circuit performs the data reading in accordance with a difference between passing currents of the first and second data lines.
Since the device according to the invention is provided with the level control circuit for changing voltages on the data lines to the predetermined level during the data reading, a time required for charging the data lines can be reduced, and the data reading can be performed fast.
According to still another aspect of the invention, a thin film magnetic memory device includes a plurality of memory cells, a reference cell, first and second data lines and a data read circuit. The plurality of memory cells are arranged in rows and columns, and each have one of first and second electric resistances corresponding to magnetically written storage data. The reference cell has an electric resistance intermediate between the first and second electric resistances. The first data line is electrically coupled between first and second voltages via the selected memory cell corresponding to a selected address among the plurality of memory cells during data reading. The second data line is electrically coupled between the first and second voltages via the reference cell during the data reading. The data read circuit performs the data reading in accordance with a difference between passing currents of the first and second data lines. Each of the first and second data lines includes bit line portions arranged corresponding to the memory cell columns, respectively, and a local data line portion arranged corresponding to the data read circuit. The thin film magnetic memory device further includes a gate circuit and precharge circuits. The gate circuit controls connection between the bit line portion and the local data line portion in accordance with a column select instruction. The precharge circuits are provided corresponding to the memory cell columns, respectively, for precharging the first and second bit lines before the data reading, and being deactivated in response to the column select instruction during the data reading.
According to the invention, therefore, the precharge circuit for precharging the bit lines is employed, and is deactivated in response to the column select instruction so that a signal line for the precharge circuit is not required. Accordingly, fast data reading can be achieved without increasing the number of parts.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.